1. Field of the Invention
This invention relates to circuits to transfer digital signals to a transmission line connecting two integrated circuits. More particularly, this invention relates to circuits that transfer digital signals to an unterminated transmission line while limiting the effects of reflections and noise on power distribution lines.
2. Description of the Related Art
Driver and receiver circuits for the transfer of digital signals between functions of an electronic or computer system are well known in the art. Bus structures such as the Integrated Drive Electronics (IDE) specified in the American National Standards Institute (ANSI) standard X3T10 describe the electrical power and data interface between a computer system board (motherboard) and an integrated disk controller. Generally these driver circuits consist of transistors configured to transfer signals from internal function circuits of the integrated circuit and to condition the signals to be transferred and to transfer the signals to an input/output pad formed at the surface of a semiconductor substrate on which the integrated circuit is formed. Attached to the input/output pad is wirebond. The wirebond is formed of a fine wire connected to the input/output pad at one end and connected to a wire trace that is formed into a bonding pad on a module on which the semiconductor die is mounted at the opposite end of the bonding wire. The wirebond allows the signal further transferred to printed wiring traces on the module. The printed wiring traces of the module are connected to terminal pins of the module. The terminal pins of the module allow the module to be mounted to a printed circuit board (the motherboard or the integrated disk controller). The pins are either connected through vias (holes in the printed circuit board) or in contact with pads formed of printed wiring traces on the surface of the printed circuit board. The pins will be generally soldered to the vias or the contact pads of the printed circuit board. The vias or contact pads are connected to printed wiring traces that conduct the signals from the integrated circuit to other integrated circuits mounted similarly to the printed circuit board. Alternately, the printed wiring traces will be connected to the terminating connector pins of one end of a cable connected to the printed circuit wiring board. The cable has a second terminating connector connected at the opposite end, which is connected to a second printed circuit wiring board. The cable then transfers the signal from the integrated circuit to printed wiring traces on the second printed circuit board. The wiring traces on the second printed circuit wiring board are connected to the vias or bonding pads having the pins of a second integrated circuit module. The pins of the second integrated circuit module are connected through module wiring traces to the module bonding pads. Wirebonds connect the module bonding pads to an input/output pad on a second semiconductor substrate having a second integrated circuit. The input/output pad is connected by interconnecting layers on the surface of the semiconductor substrate to a receiver. The receiver accepts the transferred signal and conditions it for use by the internal circuits of the second integrated circuit.
At lower frequencies, the equivalent circuit of one such signal path to transfer signals between integrated circuit functions on separate printed circuit boards is as shown in FIG. 1. The output driver is formed of the n-type metal oxide semiconductor (MOS) transistor M1 and the p-type MOS transistor M2. The drains of the n-type MOS transistor M1 and the p-type MOS transistor M2 are connected through the I/O signal pad to the load capacitor CL. The load capacitor CL is composed of the capacitances of the input/output pads on the semiconductor substrate mounted in the second integrated circuit module, wirebond from the input/output pad, the module wiring trace of the second integrated circuit module, module pins of the second integrated circuit module, printed circuit wiring traces of the printed circuit boards, the terminal connectors that attach a cable to the printed circuit boards, the distributed capacitance of the inter-connecting cable, and the input loading capacitance of the receiver.
The source of the n-type MOS transistor M1 is connected through the parasitic inductance LVss and the pad connector I/OVss to the ground reference potential. The parasitic inductance LVss is the lumped inductance of a wirebond from voltage wirebonding pad of the integrated circuit to the module pin, the module pin itself, and any of the printed circuit wiring traces, connectors, and cabling connecting the ground reference potential to the integrated circuit.
The source of the p-type MOS transistor M2 is similarly connected through the parasitic inductance LVcc and the pad connector I/OVss to the power supply voltage source Vcc. The parasitic inductance LVcc is the lumped inductance of the wirebond from the integrated circuit to the module pin of the module containing the integrated circuit, the module pin itself, and any of the printed circuit wiring traces, connectors, and cabling connecting the power supply voltage source to the integrated circuit.
The gates of the n-type MOS transistor M1 and the p-type MOS transistor M2 are connected to the internal circuit Int Ckt of the integrated circuit to receive the output signal that is to be transferred to the receiver REC. When the output signal changes from a first voltage level (i.e. 0V) to a second voltage level, (i.e. Vcc) the n-type MOS transistor M1 conducts and the p-type MOS transistor M2 ceases to conduct. Any charge present on the load capacitor CL is conducted through the n-type MOS transistor M1 to the ground reference potential.
Similarly, when the output signal traverses from the second voltage level (Vcc) to the first voltage level, the n-type MOS transistor M1 ceases to conduct and the p-type MOS transistor M2 conducts. A current is transferred from the power supply voltage source through the p-type MOS transistor M2 to charge the load capacitor CL.
At shorter physical dimensions and at lower frequencies with slower transition times, the schematic of FIG. 1 is adequate to simulate the performance of the interface. However, as the dimensions increase or the frequency of operation increases, a more accurate model, as shown in FIG. 2, must be used. In FIG. 2, the drains of the n-type MOS transistor M1 and the p-type MOS transistor M2 are connected to the transmission line TX through the input/output signal pad. The opposite end of the transmission line TX is connected to the load capacitor CL. The load capacitor CL now represents the lumped capacitance of the terminating pins of the second connector of the cable, the printed circuit wiring traces, the module pins of the second integrated circuit module, the printed wiring traces of the second integrated circuit module, the bonding wire connected to the receiver REC and the input capacitance of the receiver REC itself. The current return lines of the transmission are connected to the ground reference potential.
The transmission line effects of the driver providing or sourcing current or receiving or sinking current from an open circuit produces predictable but undesirable effects to the driver signal placed on the transmission line. The effects or reflections often cause xe2x80x9cringingxe2x80x9d or self-oscillation of the driver signal during the transitions between the first voltage level (0V) and the second voltage level (Vcc).
FIG. 3 shows the addition of a terminating resistor RT from the junction of the transmission line TX and the receiver to the ground reference potential. In this example, when the output signal VO is at the second voltage level, the p-type MOS transistor must remain conducting to keep the input of the receiver at the second voltage level (Vcc).
It is well known in the art that the terminating resistor RT can be placed from the junction of the transmission line and the input of the receiver to the power supply voltage source Vcc. Further, the terminating resistor may be a network of resistors connected to both the ground reference potential and the power supply voltage source Vcc.
The terminating resistor RT eliminates or reduces any of the noise effect due to reflections on the transmission line. Any remaining reflections are due to discontinuities in the signal path due to factors such as the terminating pins of the connectors that attach the printed circuit boards to the cable forming the transmission line.
Refer now to FIG. 4 to examine a communication interface that is made up of multiple signal paths similar to FIG. 2. In the IDE standard, the interface consists of sixteen data bits or data paths.
The interface has multiple drivers D1, D2, D3, . . . , Dn, each connected through an input/output signal pad to a transmission line Tx1, Tx2, Tx3, Txn. As described above, each transmission line is connected to a receiver. The load capacitance CL, as described above, is the wiring trace capacitance, the terminating connector capacitance, and the input capacitance of the receiver.
Each driver is configured as shown in FIG. 2. When the output signal VO is such that the n-type MOS transistor M1 is turned on and the p-type MOS transistor M2 is turned off, as described above, the charge present on the load capacitance CL is discharged through the parasitic inductor LVss. The voltage VLVss developed across the parasitic inductor LVss is proportional to the change in current resulting from the activation of the n-type MOS transistor M1. If any or all of the drivers of the communication interface have their n-type MOS transistors M1 activated, the resulting currents are added, thus increasing the level of noise or xe2x80x9cground bouncexe2x80x9d on the distribution path for the ground reference potential. This xe2x80x9cground bounce,xe2x80x9d also referred to as xcex94i noise, impacts the operation of the internal circuits as well as the drivers of the communication interface.
Alternately, when the output signal VO is such that p-type MOS transistor M2 is turned on and the n-type MOS transistor M1 is turned off, the load capacitance CL is now charged by a current from the power supply voltage source Vcc through the parasitic inductor LVcc. The voltage VLVcc across the parasitic inductor LVcc is proportional to the change in the charging current flowing to the load capacitance CL through the p-type MOS transistor M2. If any or all the drivers have their p-type MOS transistors activated, the resulting currents are added, thus increasing the level of noise or power supply xe2x80x9cbouncexe2x80x9d (again xcex94i noise) on the distribution path for the power supply voltage source. The power supply xe2x80x9cbouncexe2x80x9d or noise also affects the operation of the internal circuits as well as the drivers of the communication interface.
In order to minimize the effect of a very fast rise time on the transfer of the driver signal on the transmission line, the slew rate of the driver as measured in volts/second is lowered. It is well known in the art that if the electrical length of the transmission line TX is less than one half the rise time or fall time of the driver signal, then the transmission can be considered capacitive and included in the load capacitance CL as shown in FIG. 1.
FIG. 5 shows a complementary driving circuit of the prior art with slew rate control. The driver circuit DRV is connected to the transmission line TX as described in FIG. 2. The slew rate control predrivers SRC1 and SRC2 are connected to the driver circuit to control the activation of the driver circuit when the output signal VO indicates that the driver signal VD is to change between the first voltage level (0V) and the second voltage level (Vcc). The first and second slew rate control predrivers respectively consist of the n-type MOS transistors M3 and M5 and the p-type MOS transistors M4 and M6. The drains of the n-type MOS transistor M5 and the p-type MOS transistor M6 are connected to the gate of the n-type MOS transistor M1. The drains of the n-type MOS transistor M3 and the p-type MOS transistor M4 are connected to the gate of the p-type MOS transistor M2. The gates of the n-type MOS transistors M3 and M5 and the p-type MOS transistors M4 and M6 are connected to the internal circuits to receive the output signal. The sources of the n-type MOS transistors M3 and M5 are connected to the ground reference potential through the parasitic inductance LVSS and the voltage wirebonding pad I/OVSS. The sources of the p-type MOS transistors M4 and M6 are connected through the parasitic inductance LVCC and the voltage wirebonding pad I/OVCC to the power supply voltage source.
An example of a conventional slew rate control is provided in U.S. Pat. No. 6,081,134, the contents of which are incorporated herein by reference.
FIG. 6a illustrates the xe2x80x9cground bouncexe2x80x9d or the voltage VLVss across the parasitic inductor LVss of FIG. 5. As is shown, the voltage VLVss across the parasitic inductor LVss can change by approximately 2.5V when the driver signal VD is changing from the second voltage level (Vcc) to the first voltage level (0V) and the load capacitance CL is being discharged.
Conversely, FIG. 6b illustrates the power supply xe2x80x9cbouncexe2x80x9d or the voltage developed across the parasitic inductor LVcc of FIG. 5. In this case, the voltage VLVcc can change by approximately 600 mV when the driver signal changes from the first voltage level (0V) to the second voltage level (Vcc) and the load capacitance CL is being charged.
This noise is super-positionally added when the driver signal of multiple drivers, as shown in FIG. 4, are simultaneously traversing between the first voltage level (0V) and the second voltage level (Vcc).
Refer now to FIG. 7 to discuss the voltage at the near end or transmitter end of the transmission line. The output signal VO is transmitted to the slew rate control drivers SRC1 and SRC2 of FIG. 5. In response to the output signal VO, the output driver DRV generates the driver signal VD. The point A on the driver signal VD shows the voltage of the driver signal VD at the beginning of the transmission down the transmission line Tx. The voltage at point A on the driver signal VD is the voltage divider of the characteristic impedance Z0 of the transmission line TX and the voltage drop across the p-type MOS transistor M2. The voltage at point B on the driver signal VD is the result of the reflection from the load capacitance CL. As can be seen, the voltage at the drain of the p-type MOS transistor M2 can become negative, causing a large instantaneous current flow from the power supply voltage source Vcc. The voltage returns at point C on the driver signal VD to the voltage level of the power supply voltage source Vcc with modest xe2x80x9cringingxe2x80x9d or damped self-oscillation.
When the output signal VD changes from the second voltage level (Vcc) to the first voltage level (0V), the driver signal VD falls to the voltage level at point D. This again is a result of the voltage divider between the driver, in this case, the n-type MOS transistor M1 and the impedance of the transmission line Tx. The returning reflections cause the xe2x80x9cringingxe2x80x9d or damped self-oscillation as seen in point E on the driver signal VD.
Refer now to FIG. 8 to review the voltage levels at the far end of the transmission line Tx at the input of the receiver. The output signal VO is, as described above, transferred from the internal circuits to the slew rate control predrivers SRC1 and SRC2. In response to the output signal VO the driver signal VD at the receiver is as shown. The arrival of the incident wave of the driver signal at the load capacitance CL, which appears as an open circuit. The driver signal level VD is doubled to the voltage level at point A on the driver signal VD. Subsequent reflections cause the xe2x80x9cringingxe2x80x9d or damped self-oscillation shown at point B on the driver signal VD.
When the output signal traverses from the second voltage level (Vcc) to the first voltage level (0V), the incident wave of the driver signal VD is transmitted down the transmission line to arrive at the load capacitance. The voltage level a point D on the driver signal VD of FIG. 7 is doubled and the voltage level of point C on the driver signal VD of FIG. 8 is achieved. The attendant reflections cause the xe2x80x9cringingxe2x80x9d or damped self-oscillation shown at point D on the driver signal VD of FIG. 8.
If the frequency transmitted as the output of the internal circuit is sufficiently high and the slew rate sufficiently large, the xe2x80x9cringingxe2x80x9d or damped self-oscillation on the transmission line and the noise on the power supply distribution interconnections is sufficiently large to prevent the receiving of the digital data. The classic IDE standard has a maximum transmission rate of 8 MHz. However, as the system design has improved, it is desirable to transmit the data at 16 MHz without the xe2x80x9cringingxe2x80x9d or damped self-oscillation and the power distribution noise.
In accordance with an aspect of the present invention, a complementary self-limiting driver circuit within an integrated circuit for driving unterminated transmission lines includes a driving circuit for receiving an output signal that is changing from a first signal level (0V) to a second signal level, and after a period of time, is changing from the second signal level (approximately Vcc) to the first signal level. In response to the output signal, a driving signal is provided to an output terminal connected to the unterminated transmission line. A first limiting circuit is connected to the driving means for controlling a slew rate of the driving means when the driver signal is changing from the first signal level to the second signal level and for disabling the driving means when the output signal approaches within a threshold level of the second signal level. A second limiting circuit is optionally connected to the driving means for controlling the slew rate of the driving means when the driver signal is changing from the second signal level to the first signal level and for disabling the driving means when the output signal approaches within a threshold level of the first signal level.
The driving circuit has a first transistor of a first conductivity type. The first transistor of a first conductivity type has a first terminal connected to receive the output signal, a second terminal connected to the output terminal for providing the output signal during the changing from the first signal level to the second signal level, and a third terminal connected to a reference voltage source. The driving circuit also has a first transistor of a second conductivity type. The first transistor of a second conductivity type has a first terminal connected to receive the output signal, a second terminal connected to the output terminal for providing the output signal during the changing from the second signal level to the first signal level, and a third terminal connected to a power supply voltage source.
The first limiting circuit is composed of a second transistor of the first conductivity type. The second transistor of the first conductivity type has a first terminal connected to the driving means, a second terminal connected to the internal circuits to receive the output signal, and a third terminal connected to the reference voltage source. The first limiting circuit has a second transistor of the second conductivity type. The second transistor of the second conductivity type has a first terminal connected to the output terminal, a second terminal connected to the internal circuits to receive the output signal, and a third terminal connected to the first terminal of the second transistor of the first conductivity type and to the driving means such that when the output signal activates the driving means, the driving means is functioning as a diode until the driver signal achieves a signal level within the threshold of the first signal level at which time the driving means is disabled.
The second optional limiting circuit is composed of a third transistor of the second conductivity type. The third transistor of the second conductivity type has a first terminal connected to the driving means, a second terminal connected to the internal circuits to receive the output signal, and a third terminal connected to the power supply voltage source, The second limiting circuit also has a third transistor of the first conductivity type. The third transistor of the first conductivity type has a first terminal connected to the output terminal, a second terminal connected to the internal circuits to receive the output signal, and a third terminal connected to the first terminal of the third transistor of the second conductivity type and to the driving means such that when the output signal activates the driving means, the driving means is functioning as a diode until the driver signal achieves a signal level within the threshold of the second signal level at which time the driving means is disabled.
In order to provide a D.C current level necessary for terminated transmission lines or for receiver requiring a minimum current level, The complementary self-limiting driver circuit further includes a current driving means connected in parallel with the driving circuit. The current driving means also receives the output signal from the internal circuits and in response to the output signal provides a path to source and sink current from the output terminal.
For communication interfaces having a higher voltage level than can be tolerated by the transistors of the complementary self-limiting driver circuit, a cascode driving circuit is placed between the driving means and the output terminal. The cascode driving circuit restricts a high voltage present at the output terminal from contacting the driving means and damaging the driving means. The cascode driving means is formed of a fourth transistor of the first conductivity type, and a fourth transistor of the second conductivity type. The fourth transistor of the first conductivity type has a first terminal connected to the output terminal, a second terminal connected to the driving means, and a third terminal connected to a first biasing voltage source. The fourth transistor of the second conductivity type has a first terminal connected to the output terminal, a second terminal connected to the driving means, and a third terminal connected to a second biasing voltage source.